module ram_controller 
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=6)
(
	input clk, wen,
	input [ADDR_WIDTH-1:0] addr,
	input [DATA_WIDTH-1:0] data,
	output [DATA_WIDTH-1:0] q
);
	
	single_port_ram_memory 
	#(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) ram_mem(
		.clk(clk),
		.we(wen),
		.data(data),
		.addr(addr),
		.q(q)
	);	


endmodule
